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Altera_Forum's avatar
Altera_Forum
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11 years ago

Clock enable design meets timing, but fails runtime

I have a 250Mhz clock generating a 125Mhz clock enable. All the logic runs of the 250Mhz with the 125Mhz clock enable at all registers. The design meets timing, but I see mixed results during runti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Are you getting some strange behavior/synthesis results because your enable and reset are in your sensitivity list but being treated synchronously to clk250 inside your process?

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I can remove the reset and enable from the sensitivity list and try the change. I do know that the reset and enable is not changing, causing the weird counting pattern.

Thanks, I give it a try. I stumped.