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Altera_Forum's avatar
Altera_Forum
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11 years ago

Clock enable design meets timing, but fails runtime

I have a 250Mhz clock generating a 125Mhz clock enable. All the logic runs of the 250Mhz with the 125Mhz clock enable at all registers. The design meets timing, but I see mixed results during runti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The clock input for signal tap is the 250Mhz clock, but I also added the 125Mhz clock enable as a reference. All the _tp signals are the actual signals run through a register to ease timing. Helps with loading of signals for signaltap.

I would post more code, but the failures varies throughout the project. Should I be concerned about the phase relatationship of the 250 and 125 clock enable, or should the tool take care of that?

Is it possible a SDC constraint is causing this?