Clock and Gain (Width) in VHDL

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Hello friends,

recently, i have been asking questions on this forum. Pls dont get upset at my questions if they are too elementary. This is because i'm new to this area and i've got a deadline for my final project.

Again i like to ask, programming VHDL in quartus II... Where exactly does one set the actual clock and gain value for a comparator? Is it at the wave vector or in the VHDL code itself. I understand this could be done in the wave vector, for simulation (synthesis). But for the actual implementation in a Stratix iii device, are the wave vector values still valid??? Cos it seems to me that only the VHDL code is loaded into the device and not with the wave vector value. pls clarify me on this.

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you better tell us what you want to design; a comparator of two inputs? one input set to a constant? forget about clock now as that is the easy bit. Also forget about simulation waveforms as it has nothing to do with implementation. You implement first then simulate and not the other way round.

I meant Programming the device when i said "implement". the VHDL code has been writing and i have simulated successfully. But am using a comparator in the design to compare inputs (2) of width 16 each. one of the input has a fixed width, so i like to know if the width (gain) will remain at the wave vector which i set for a quick simulation or i have to do that on my VHDL code. if its VHDL can u give me an idea (syntax) of how to assign a specific value (not bit, but unsigned decimal) to an input of a comparator.

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you better tell us what you want to design; a comparator of two inputs? one input set to a constant? forget about clock now as that is the easy bit. Also forget about simulation waveforms as it has nothing to do with implementation. You implement first then simulate and not the other way round.

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If I understood you, you are simulating your design by comparing your output with some reference value(or comparing two items?). I can answer your last question.

Instead of eye checks on waveforms you can run a testbech (vhdl program around your design that gives inputs to your design and checks its outputs). In the testbench to assign a value to std_logic_vector you need to add ieee.numeric_std.all; then

data <= std_logic_vector(to_unsigned(20000,16)); -- assigns 20000 to your 16 bit data

if you wish you can just directly assign to it bit patterns of 20000 instead

Thanks, am going to try that right away.. and i'll get back to u later

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If I understood you, you are simulating your design by comparing your output with some reference value(or comparing two items?). I can answer your last question.

Instead of eye checks on waveforms you can run a testbech (vhdl program around your design that gives inputs to your design and checks its outputs). In the testbench to assign a value to std_logic_vector you need to add ieee.numeric_std.all; then

data <= std_logic_vector(to_unsigned(20000,16)); -- assigns 20000 to your 16 bit data

if you wish you can just directly assign to it bit patterns of 20000 instead

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