Clock and Gain (Width) in VHDL

Thanks, am going to try that right away.. and i'll get back to u later

--- Quote Start ---

If I understood you, you are simulating your design by comparing your output with some reference value(or comparing two items?). I can answer your last question.

Instead of eye checks on waveforms you can run a testbech (vhdl program around your design that gives inputs to your design and checks its outputs). In the testbench to assign a value to std_logic_vector you need to add ieee.numeric_std.all; then

data <= std_logic_vector(to_unsigned(20000,16)); -- assigns 20000 to your 16 bit data

if you wish you can just directly assign to it bit patterns of 20000 instead

--- Quote End ---