Clock and Gain (Width) in VHDL

I meant Programming the device when i said "implement". the VHDL code has been writing and i have simulated successfully. But am using a comparator in the design to compare inputs (2) of width 16 each. one of the input has a fixed width, so i like to know if the width (gain) will remain at the wave vector which i set for a quick simulation or i have to do that on my VHDL code. if its VHDL can u give me an idea (syntax) of how to assign a specific value (not bit, but unsigned decimal) to an input of a comparator.

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you better tell us what you want to design; a comparator of two inputs? one input set to a constant? forget about clock now as that is the easy bit. Also forget about simulation waveforms as it has nothing to do with implementation. You implement first then simulate and not the other way round.

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