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ashbinbabu's avatar
ashbinbabu
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1 year ago
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CFM0 Overlaps with Configuration Data (Error 20646 Quartus Prime)

Hi, We are using 10M25 for the design of our PFR enabled FPGA code for a server motherboard. Here we have partitioned CFM0 for recovery image and CFM1 for the active image. We had a reference design...
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  • FvM's avatar
    FvM
    1 year ago

    Hi,
    obviously, userdata start addresses of 0x41000 and 0x83000 are not suitable for 10m25 flash layout. If you want to keep the distance from CFM1 and CFM0 end address (-0x9000) , they should be changed to 0x5b000 and 0xb7000.

    P.S.: I don't work with NIOS II and am not aware of the relation between start adresses and vectors shown in post #1 for 10m16. But basically everything should be relocated according to increased CFM1 and CFM0 flash size.

    Regards

    Frank

ashbinbabu's avatar
ashbinbabu
Icon for New Contributor rankNew Contributor
1 year ago

Hi Aiman,

We do know the reason for the error. But how to correct this?

Let me give a detailed explanation about the problem below:

  1. In our design, we are using 10M25 device instead of 10M16 compared to in our reference design.
  2. we are reusing the reset vector offset, exception vector offset etc. as per the reference design itself. Pls see the below images for reference.

  1. Pls see the below image showing the flash layout:

  1. Here we could notice that the address mapping of CFM is different from that of reference design probably because of the change in device.
  2. Now we have compiled and generated the .sopcinfo file from platform designer for both pfr and recovery.
  3. We created a BSP project from this .sopcinfo file
  4. Using this settings.bsp, we created the .hex file for both pfr and recovery using the commands below:

alt-file-convert -I elf32-littlenios2 -O hex --input=recovery_app.elf --output=recovery_code.hex --base=0x00182000 --end=0x0018bfff --reset=0x00182000 --out-data-width=8 --boot="C:/intelFPGA_lite/18.1/nios2eds/components/altera_nios2/boot_loader_cfi.srec"

alt-file-convert -I elf32-littlenios2 -O hex --input=pfr_app.elf --output=pfr_code.hex --base=0x00140000 --end=0x0018bfff --reset=0x00140000 --out-data-width=8 --boot="C:/intelFPGA_lite/18.1/nios2eds/components/altera_nios2/boot_loader_cfi.srec"

  1. While creating both BSP and .hex files, we didnt change any addresses and offsets and reused everything that was used in the reference design which used 10M16. For example, the base, end, reset addresses in the above commands were reused.
  2. Now on creating a .pof file in Quartus, we are using the following settings. Pls see the image below:

  1. However, on generating .pof file, we are getting an error as follows:

-" Error (20646): The page CFM0 user data requested start address 0x00083000 overlaps with configuration data that end at address 0x000A3767."

  1. What could be the reason for this? When the device is changed, should the reset vector offsets also need to be changed? Pls let us know how if it is to be changed.
  2. Should we change the other addresses which we use during BSP generation and .hex file creation as well? Let us know if it is required.
  3. Pls let us know the actual cause for this and how to avoid this issue so that we can successfully create the .pof file.

Regards,

Ashbin