CDC Interconnect in Platform Designer

Hello community,

I have several custom DSP blocks that expose an AXI4-Lite CSR interface for system control and monitoring. These registers need to be accessed from the HPS (bare-metal/Yocto) via the H2F lightweight AXI bridge. The H2F LW bridge operates on a 100 MHz clock, while the AXI4-Lite interfaces inside the DSP blocks are synchronous to a separate DSP clock that is asynchronous to the 100 MHz domain.

I am currently using the Intel AXI interconnect in Platform Designer to connect the LW bridge to the DSP blocks, and I’ve observed that No clock-domain crossing logic is being inserted between the LW bridge and the DSP AXI interfaces.

My question is: does Platform Designer provide an interconnect mechanism (similar to Xilinx AXI interconnects) that allows connecting AXI master and slave interfaces in different clock domains and automatically handles the required CDC logic? Or is explicit CDC handling required at the AXI slave interface level for this use case? Any guidance or best practices would be greatly appreciated.