Honored ContributorHi,
Is there any way to set values to parameter or generic in Verilog/VHDL RTL code with the Quartus II? I want to change the parameters inside megacore without modifting RTL code. Thanks
Honored ContributorIn the Assignment Editor, select "Parameters" near the bottom of the "Category" list. I think this will override parameters explicitly set in the RTL, but I don't remember for sure.
Honored ContributorHere's by far the most common usage of it, which is used when a piece of IP targets a specific RAM type and the end user wants to force it to a different type:
http://www.altera.com/support/kdb/solutions/rd02172004_713.html?gsa_pos=6&wt.oss_r=1&wt.oss=m4k%20m-ramHonored ContributorHi Brad and Rysc,
I appreciate your answer. It looks work well. RegardsHonored ContributorDigging an old one up here.
Does anybody now how this translates to assignments in the qsf? I'm trying to change the value of a top level block VHDL generic in different build revisions. Thanks.Honored Contributori've used VHDL packages for that (you could call in different packages with the .qsf or other build script)
however, here's the parameter in the .qsf: set_parameter -name my_param my_valueHonored ContributorYes changing a package in the qsf would be an option but we potentially have many variations (based on the generic) of the same build and hence many qsfs. So what we are going to do is set up the project with a bash script that changes the single paramater setting in some tcl accordingly, and then runs the tcl to set up the project.
I've got a top level called "fred_top" with a generic called "width" which by default is 8. What I try and do is change that value by setting the following in the qsf but unfortunaletly it doesn't seem to work.set_parameter -name width 16 -to fred_topi will see if i can test the Quartus parameters instead of VHDL packages
if you're really stuck you could make the bash script generate the VHDL package on the fly based on the parametrization (same .vhd name so no changes to .qsf)Honored ContributorPancake,
This is some code I knocked up to test it...
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fred is
generic ( frog : integer := 1 );
port (
in1 : in std_ulogic_vector (3 downto 0);
in2 : in std_ulogic_vector (3 downto 0);
sel : in std_ulogic_vector (3 downto 0);
out1 : out std_ulogic_vector (3 downto 0));
end fred;
architecture RTL of fred is
--
component mx_comp_1
port(
in1 : in std_ulogic;
in2 : in std_ulogic;
sel : in std_ulogic;
out1 : out std_ulogic);
end component;
--
component mx_comp_2
port(
in1 : in std_ulogic;
in2 : in std_ulogic;
sel : in std_ulogic;
out1 : out std_ulogic);
end component;
begin
GEN: for n in 3 downto 0 generate
COND1 : if (frog = 1) generate
mx1g : mx_comp_1
port map (
in1 => in1(n),
in2 => in2(n),
sel => sel(n),
out1 => out1(n)
);
end generate;
COND2 : if (frog = 2) generate
mx2g : mx_comp_2
port map (
in1 => in1(n),
in2 => in2(n),
sel => sel(n),
out1 => out1(n)
);
end generate;
end generate;
end RTL;
set_parameter -name frog 2 -to fredIt work's exactly as suggested above:
--- Quote Start --- set_parameter -name my_param my_value --- Quote End --- Please consider, that in VHDL parameters can be only set for the top entity, not down the hierarchies. Thus the set_parameter tcl command doesn't need/understand an entity name here.Honored ContributorFvM brilliant, thanks.
It seems all I had to do is drop the -to option. Just using this works...set_parameter -name frog 2 
