Forum Discussion
Altera_Forum
Honored Contributor
15 years agoPancake,
This is some code I knocked up to test it...
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fred is
generic ( frog : integer := 1 );
port (
in1 : in std_ulogic_vector (3 downto 0);
in2 : in std_ulogic_vector (3 downto 0);
sel : in std_ulogic_vector (3 downto 0);
out1 : out std_ulogic_vector (3 downto 0));
end fred;
architecture RTL of fred is
--
component mx_comp_1
port(
in1 : in std_ulogic;
in2 : in std_ulogic;
sel : in std_ulogic;
out1 : out std_ulogic);
end component;
--
component mx_comp_2
port(
in1 : in std_ulogic;
in2 : in std_ulogic;
sel : in std_ulogic;
out1 : out std_ulogic);
end component;
begin
GEN: for n in 3 downto 0 generate
COND1 : if (frog = 1) generate
mx1g : mx_comp_1
port map (
in1 => in1(n),
in2 => in2(n),
sel => sel(n),
out1 => out1(n)
);
end generate;
COND2 : if (frog = 2) generate
mx2g : mx_comp_2
port map (
in1 => in1(n),
in2 => in2(n),
sel => sel(n),
out1 => out1(n)
);
end generate;
end generate;
end RTL;
If you manually change the frog generic from 1 to 2 it changes which mx_comp is generated in Quartus, as you would expect. Nw to do this is the qsf I used... set_parameter -name frog 2 -to fred In this case fred is the top level. It did not work. Now either I'm doing something wrong or it's simply not working. Thanks for your effort on this.