New ContributorCan I use priority/unique modifiers on if statement?
Hi, hopefully a quick question, I am programming a decoder with a series of if-else statements, and I want to tell the synthesis tool that all clauses should be evaluated in parallel, for that I know that I can add the "unique" modifier to the first if (as stated in section 7.10.1 of this book: https://link.springer.com/book/10.1007/0-387-36495-1), but when I try to run the "analysis & synthesis" process I get back the following error (Quartus Prime Version 23.1 std.0 Build 991 11/28/2023 SC Lite Edition):
"10170 Verilog HDL syntax error at codificador_prioridad.sv(8) near text: 'if'; expecting 'case' ..."
So, does this mean that the tool does not implement such syntax? Or it is not a supported syntax in Systemverilog (e.g. the book is lying)? Or is that the standard implemented by the tool is not updated?
Kind Regards
It might help if you show the relevant lines of the .sv file under question.
Otherwise we are just shooting in the dark not knowing exactly what you coded.
There is this tho ... https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/mapIdTopics/jka1465580571884.htm
