Forum Discussion
Jacobinho86
New Contributor
New ContributorCan I use priority/unique modifiers on if statement?
Hi, hopefully a quick question, I am programming a decoder with a series of if-else statements, and I want to tell the synthesis tool that all clauses should be evaluated in parallel, for that I know...
It might help if you show the relevant lines of the .sv file under question.
Otherwise we are just shooting in the dark not knowing exactly what you coded.
There is this tho ... https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/mapIdTopics/jka1465580571884.htm
sstrell
Super Contributor
Super ContributorAs mentioned, unique is only for case statements since more than one condition can match with a Verilog case statement. if-else implies a priority encoder so that is not what you want. You should be using a case statement and if there is the possibility of more than one condition matching the expression you are evaluating, then you can add unique to it.
