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Altera_Forum's avatar
Altera_Forum
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16 years ago

Calling a module within an always block

I'm a java coder to begin with so sometimes verilog can be confusing at times and this is one of those times. What I'm trying to do is to call a module inside an if that is inside an always block. When I try to do that it gives me an error that says "task 'module_name' is not used as a task".

I know that I can just copy and paste everything from that module that I need and make it into a task. But inside that module, I also use another module. There are other modules used inside that module as well.

So what is a "proper" way to call a module inside an if?

Any help would be greatly appreciated. Thank you.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    So what is a "proper" way to call a module inside an if?

    --- Quote End ---

    There is simply no way. Actually, a Verilog module respectively a VHDL component is a an independent logic unit, it isn't called rather than instantiated.

    As you mentioned at the beginning, FPGA programming with hardware description languages is different from a procedural programming of a processor.

    If you want an external signal to modify the logical behaviour of a module, possibly stop it's operation, this must be achieved somehow through the module's ports. In case of a clocked module, a clock enable can be e.g. cut off.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Probably best to talk about what you are trying to do.

    1 - Are you synthesizing or simulating?

    2 - You have three constructs in Verilog for subdividing functionality

    a - Modules

    b - Functions

    c - Tasks

    You may be able to accomplish what you are trying to accomplish using a task or a function. You can NOT normally call a module from within an "if" statement. The one exception to this is if you are using a "generate if" but I don't think that's what you are trying to do.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If anyone is searching for the answer, here is the link to the best answer

    electronicspoint.com/calling-modules-always-block-verilog-t22145.html ( I cant post the link)

    In case if the link is not working, instantiate the calling module outside the 'always' block, and set the register values inside the always block.

    For example, I want to call this module in the always block, for that I can do the following ram_dp framebuffer1 (.CLK(CLOCK_50),

    .WE(we), .read_address(h_count_reg*800+v_count_reg), .write_address(h_count_reg*800+v_count_reg),

    .input_data(1'b1)//,

    .output_data(ram_dataout)

    );

    inside the always block , set the value of 'we' , its working for me.

    Thanks.:evil: