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So what is a "proper" way to call a module inside an if?
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There is simply
no way. Actually, a Verilog module respectively a VHDL component is a an independent logic unit, it isn't
called rather than
instantiated.
As you mentioned at the beginning, FPGA programming with hardware description languages is different from a procedural programming of a processor.
If you want an external signal to modify the logical behaviour of a module, possibly stop it's operation, this must be achieved somehow through the module's ports. In case of a clocked module, a clock enable can be e.g. cut off.
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