Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Calling a module within an always block

I'm a java coder to begin with so sometimes verilog can be confusing at times and this is one of those times. What I'm trying to do is to call a module inside an if that is inside an always block. Wh...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Probably best to talk about what you are trying to do.

1 - Are you synthesizing or simulating?

2 - You have three constructs in Verilog for subdividing functionality

a - Modules

b - Functions

c - Tasks

You may be able to accomplish what you are trying to accomplish using a task or a function. You can NOT normally call a module from within an "if" statement. The one exception to this is if you are using a "generate if" but I don't think that's what you are trying to do.

Jake