Bug report have lost during the to migration myAltera to Intel website. How can I find this report?

Hi,

I have taken a look at your codes,

Second sample of code that compiles in modelsim is correct, it does compile in Quartus Prime Pro edition as well.

Similarly Quartus Prime pro edition gives Error on first sample of code you shared.

Quartus Prime Lite/ Standard edition has limited support for system verilog, however Quartus Prime Pro edition fully support system verilog.

You may refer to Quartus prime comparison sheet for this information.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf

Thanks,

Arslan

Hi IIvan3,

Can you post the error message and syntax that you are seeing the error during compilation in Quartus and ModelSim-Altera? Then we may be able to provide the appropriate assistance to your issue. Or are you asking the details description of the SR#: 11416142 that was submitted previously?

Regards,

Nooraini

I am asking about report #11416142 whitch mast be already exist. But I do not see them in myAltera.

1) This code compile in Quartus without any errors:

module top_module (output [7:0]my_out);
	struct{enum{STAGE_1, IDLE} FSM;
			 logic some_register;} first_machine;
	struct{enum{STAGE_2, IDLE} FSM;
			 logic some_register;} second_machine;	
			
	assign my_out = first_machine.IDLE;
	
endmodule

But in ModelSim-Altera this code causes an error:

# ** Error: D:/Intel_Altera/Altera_projects/LITERAL/LITERAL.sv(6): Enum literal name 'IDLE' already exists.

2) This code compile in ModelSim-Altera without any errors:

module top_module (output [7:0]my_out);
	struct{enum{STAGE_1, IDLE_1} FSM;
			 logic some_register;} first_machine;
	struct{enum{STAGE_2, IDLE_2} FSM;
			 logic some_register;} second_machine;	
			
	assign my_out = IDLE_1;
	
endmodule

But in Quartus this code causes an error:

Error (10161): Verilog HDL error at LITERAL.sv(25): object "IDLE_1" is not declared. Verify the object name is correct. If the name is correct, declare the object.

3) This code compile in Quartus without any errors:

module top_module (output [7:0]my_out);
	struct{enum{STAGE_1, IDLE_1} FSM;
			 logic some_register;} first_machine;
	struct{enum{STAGE_2, IDLE_2} FSM;
			 logic some_register;} second_machine;	
			
	assign my_out = first_machine.IDLE_1;
	
endmodule

But in ModelSim-Altera this code causes an error:

# ** Error: D:/Intel_Altera/Altera_projects/LITERAL/LITERAL.sv(25): Field/method name (IDLE_1) not in 'first_machine'

---

So, it's impossible to simulation with ModelSim-Altera and using enum inside struct.

In my opinion Quartus understanding of Verilog standard is more usable.

I want understand Intel(Altera) position. Can they force Mentor to good understanding of Verilog standard? Will they do it?

Hi IIvan3,

@mteh​

Apologize for the delay, I checked the SR#11416142 however this SR status has been closed during the migration process to IPS system. Currently myAltera no longer exist but has been migrate to my Intel account. I will try to assign/find someone to assist you on this thread. Thank you.

Regards,

Nooraini

Thank you.