Bug report have lost during the to migration myAltera to Intel website. How can I find this report?

I am asking about report #11416142 whitch mast be already exist. But I do not see them in myAltera.

1) This code compile in Quartus without any errors:

module top_module (output [7:0]my_out);
	struct{enum{STAGE_1, IDLE} FSM;
			 logic some_register;} first_machine;
	struct{enum{STAGE_2, IDLE} FSM;
			 logic some_register;} second_machine;	
			
	assign my_out = first_machine.IDLE;
	
endmodule

But in ModelSim-Altera this code causes an error:

# ** Error: D:/Intel_Altera/Altera_projects/LITERAL/LITERAL.sv(6): Enum literal name 'IDLE' already exists.

2) This code compile in ModelSim-Altera without any errors:

module top_module (output [7:0]my_out);
	struct{enum{STAGE_1, IDLE_1} FSM;
			 logic some_register;} first_machine;
	struct{enum{STAGE_2, IDLE_2} FSM;
			 logic some_register;} second_machine;	
			
	assign my_out = IDLE_1;
	
endmodule

But in Quartus this code causes an error:

Error (10161): Verilog HDL error at LITERAL.sv(25): object "IDLE_1" is not declared. Verify the object name is correct. If the name is correct, declare the object.

3) This code compile in Quartus without any errors:

module top_module (output [7:0]my_out);
	struct{enum{STAGE_1, IDLE_1} FSM;
			 logic some_register;} first_machine;
	struct{enum{STAGE_2, IDLE_2} FSM;
			 logic some_register;} second_machine;	
			
	assign my_out = first_machine.IDLE_1;
	
endmodule

But in ModelSim-Altera this code causes an error:

# ** Error: D:/Intel_Altera/Altera_projects/LITERAL/LITERAL.sv(25): Field/method name (IDLE_1) not in 'first_machine'

---

So, it's impossible to simulation with ModelSim-Altera and using enum inside struct.

In my opinion Quartus understanding of Verilog standard is more usable.

I want understand Intel(Altera) position. Can they force Mentor to good understanding of Verilog standard? Will they do it?