[BUG]: Platform-Designer generates invalid .dtso-file (multiple interrupts not possible)

Hi

I believe that you are using the sopc2dts converter to generate the device tree file from the sopc file info?

Sorry to say that we have discontinued the sopc2dts converter. The device tree would need to be created or edited base on our GSRD package.

Regards

Jingyang, Teh

Hi

Do you have any follow up question regarding this case?

Regards

Jingyang, Teh

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh

reopening the case

Hi

Yeah Sure.

There are plenty of how to in editing the device tree online.

For the interrupt cell below are the explaination on the entery:

• The 1st cell is the interrupt type: 0 for SPI interrupts, 1 for PPI interrupts.
• The 2nd cell contains the interrupt number for the interrupt type.

SPI interrupts are in the range [0-987], PPI interrupts are in the range [0-15]

• The 3rd cell is the flags, encoded as follows:
• bits[3:0] trigger type and level flags.
• 1 = low-to-high edge triggered
• 2 = high-to-low edge triggered
• 4 = active high level-sensitive
• 8 = active low level-sensitive
• bits[15:8] PPI interrupt cpu mask.

Regards

Jingyang, Teh

Hi

For the current method, the device tree of the devkit have been uploaded to the uboot branch below:

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2024.04/arch/arm/dts/socfpga_cyclone5_socdk.dts

In the device tree all the peripheral node have been created base on the Cyclone5 dev kit.

Regards

Jingyang, Teh

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh

case reopening

reopening the case

Hi

For the GSRD device tree could be found under the github link below:

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2024.04/arch/arm/dts/socfpga_cyclone5_socdk.dts

The device tree created is based on the CycloneV dev kit. You could enable and disable any node t

hat is available base on your custom board.

Regards

Jingyang, Teh