Honored ContributorI have two Qsys designs, A and B. Qsys A want to make MM Master transfer of data to memory hosted by Qsys B. A and B have different clocks. Due to complexity I don't want to put A and B into some "parent" Qsys or into the other. The question is: Is there any bridges for me? One Slave bus bridge and another Master bus bridge with FIFO built in? Can I use some of the standard IP? :confused:
Honored Contributoruse a clock crossing bridge in one, export the master port, use a pipelined bridge in the other and export the slave.
you will not however have any address information in the system.h files for the other system. i would still just instantiate both qsys systems with the above exports in a qsys system.Honored ContributorLast time I checked the clock crossing bridge (in Qsys) had an option for symbol (byte) or word addressing. If you switch both bridges to use symbol addressing then you should be able to connect them together directly and not worry about shifting address bits around.
One of your systems will need to be exposed to the clock of the other system because it will be needed to drive the exported port of the clock crossing bridge. So really you can just use one clock crossing bridge and one pipeline bridge in the other system. Note that the pairing of two bridges will only let you drive transactions in one direction, if each system has to master the other then use two pairs of bridges to do this. This is probably a no-duh comment but make sure you give each system a different name, otherwise you'll have name space collisions all over the place when compiling the hardware.
