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Altera_Forum's avatar
Altera_Forum
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14 years ago

Bridge between two Qsys designs

I have two Qsys designs, A and B. Qsys A want to make MM Master transfer of data to memory hosted by Qsys B. A and B have different clocks. Due to complexity I don't want to put A and B into some "p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

use a clock crossing bridge in one, export the master port, use a pipelined bridge in the other and export the slave.

you will not however have any address information in the system.h files for the other system. i would still just instantiate both qsys systems with the above exports in a qsys system.