Bi Directional pins

You don't drive the entity correctly. Show your test bench.

Here is the testbench. I updated it to add initial condition for the inp and outp signals, but it still does not work.

you are driving bidir with Z and also enabling the tristate to pass input. That is not right.

I tried it without driving bidir at all and it still does not work.

I note your clock is 1 us period but your waits are 500 then 1000 or so ns. You may run into sampling troubles (delta delay etc.)

Thanks Kaz I don't think its a sampling problem. For example the inp to a register and outp to b register all works fine.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY bidir IS
    PORT(
        bidir   : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        oe, clk : IN STD_LOGIC;
        inp     : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        outp    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END bidir;
ARCHITECTURE maxpld OF bidir IS
SIGNAL  a  : STD_LOGIC_VECTOR (7 DOWNTO 0);  -- DFF that stores 
                                             -- value from input.
SIGNAL  b  : STD_LOGIC_VECTOR (7 DOWNTO 0);  -- DFF that stores 
BEGIN                                        -- feedback value.
    PROCESS(clk)
    BEGIN
    IF clk = '1' AND clk'EVENT THEN  -- Creates the flipflops
        a <= inp;                    
        outp <= b;                  
        END IF;
    END PROCESS;    
    PROCESS (oe,a,b,bidir)          -- Behavioral representation 
        BEGIN                    -- of tri-states.
        IF( oe = '0') THEN
            bidir <= "ZZZZZZZZ";
            b <= bidir;
        ELSE
            bidir <= b; 
            b <= a;
        END IF;
    END PROCESS;
END maxpld;

Thanks Kaz, looks like you changed the sensitivity list for the second process.

There is more changes than just sensitivity list. see assignment when oe is not zero

Kaz, I wanted to follow up. Your code changes work perfectly and have been verified in hardware.