Bi Directional pins

Here is the testbench. I updated it to add initial condition for the inp and outp signals, but it still does not work.

In this code I was only trying to send a signal to the inp and have it appear on the bidir.

Thanks for your help!

library ieee;

use IEEE.STD_LOGIC_1164.ALL, ieee.numeric_std.all;

entity bidir_test is

end entity bidir_test;

architecture verify of bidir_test is

component bidir

PORT(

bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);

oe, clk : IN STD_LOGIC;

inp : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

outp : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));

end component;

constant clk_period : time := 1 us;-- 1Mhz clock

signal clk, oe: std_logic;

signal inp, outp: std_logic_vector (7 downto 0):= "00000000";

signal bidir1: std_logic_vector (7 downto 0):= "ZZZZZZZZ";

begin

uut: bidir Port Map (bidir => bidir1, inp => inp, outp => outp, oe => oe, clk => clk);

clk_process: process

begin

clk <= '0';

wait for clk_period/2; --for 0.5 ns signal is '0'.

clk <= '1';

wait for clk_period/2; --for next 0.5 ns signal is '1'.

end process;

test_case: process is

begin

wait for 500 ns;

oe <= '1';

bidir1 <= "ZZZZZZZZ";

inp <= "11111111";

wait for 1000 ns;

oe <= '1';

bidir1 <= "ZZZZZZZZ";

inp <= "11111111";

wait for 1000 ns;

oe <= '1';

bidir1 <= "ZZZZZZZZ";

inp <= "00000000";

wait for 1000 ns;

oe <= '1';

bidir1 <= "ZZZZZZZZ";

inp <= "00000000";

end process test_case;

end architecture verify;