Hello, I am wondering what is the best way to interface my 32-bit RISC CPU. I need to interface it with the sdram memory, the flash memory, and possibly the sram memory. I will also need to dedicate a portion of the memory to a VGA controller which will output a video signal. I am wondering what is the best method to achieving this. I looked into possibly using QSYS to setup this config, (JUST replace the NIOS 2 processor with mine) however I am not sure if I should do it due to the amount of work it will take to set up the processor interfaces (I am also going to update the CPU all the time so I will need to pick a method that will make updating all the components easy). I looked into doing it in VHDL, but I am not sure if it will be easy. I already got a VGA controller working however I will need to make the memory controllers which will be much more difficult. I forgot to include this, but I am using a terasic de1 board currently. Can somebody please help me solve this ordeal?

You can make your CPU have a Avalon master interface,then you can interface it with Avalon bus.Qsys have memory controller,you can use them to control the offchip memory.Maybe you need update the VGA controller to interface with the Avalon bus.

I am not sure if that will allow me to continually update my CPU without being forced to make a new component every time. Can somebody elaborate the process of making a custom CPU work with QSYS.

--- Quote Start --- I am not sure if that will allow me to continually update my CPU without being forced to make a new component every time. Can somebody elaborate the process of making a custom CPU work with QSYS. --- Quote End --- Assuming your CPU has some form of external bus interface that is not quite an Avalon-MM master interface, you will need to create a bridge component that maps your CPU bus into an Avalon-MM interface. That bridge would export (via conduit signals) your CPU bus to the top-level of the design. The top-level of the design would contain the Qsys system (which includes the bridge), and your CPU. As you iterate on your CPU design, the Qsys system remains identical. To design your CPU bus-to-Avalon-MM bridge, you should create a bus functional model (BFM) for your CPU bus. You can then create a testbench for your bridge logic and the Qsys system. You can then go back to your CPU design, knowing that the Qsys system has already been verified to work with your expected CPU cycles. Cheers, Dave

I did not implement any outputs yet so should I create a bridge or should I base my outputs on the Avalon-MM interface?

--- Quote Start --- I did not implement any outputs yet so should I create a bridge or should I base my outputs on the Avalon-MM interface? --- Quote End --- Yes, you could implement your CPU interface according to the Avalon-MM specification. While working on your CPU, you might want to consider keeping your CPU external to the Qsys system, i.e., the Avalon-MM master interface would be exported to the top-level of the Qsys system. This allows you to iterate on the CPU design without having to regenerate the Qsys system. Qsys has this annoying feature, where it copies source files into various synthesis and simulation directories. Keeping your CPU external to the Qsys system would avoid having multiple copies of your CPU design files. Cheers, Dave

Best way to interface my CPU | Altera Community

47 Replies

Altera_Forum
Honored Contributor
13 years ago
You can make your CPU have a Avalon master interface,then you can interface it with Avalon bus.Qsys have memory controller,you can use them to control the offchip memory.Maybe you need update the VGA controller to interface with the Avalon bus.
Altera_Forum
Honored Contributor
13 years ago
I am not sure if that will allow me to continually update my CPU without being forced to make a new component every time. Can somebody elaborate the process of making a custom CPU work with QSYS.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
I am not sure if that will allow me to continually update my CPU without being forced to make a new component every time. Can somebody elaborate the process of making a custom CPU work with QSYS.
--- Quote End ---

Assuming your CPU has some form of external bus interface that is not quite an Avalon-MM master interface, you will need to create a bridge component that maps your CPU bus into an Avalon-MM interface. That bridge would export (via conduit signals) your CPU bus to the top-level of the design.

The top-level of the design would contain the Qsys system (which includes the bridge), and your CPU. As you iterate on your CPU design, the Qsys system remains identical.

To design your CPU bus-to-Avalon-MM bridge, you should create a bus functional model (BFM) for your CPU bus. You can then create a testbench for your bridge logic and the Qsys system.

You can then go back to your CPU design, knowing that the Qsys system has already been verified to work with your expected CPU cycles.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
I did not implement any outputs yet so should I create a bridge or should I base my outputs on the Avalon-MM interface?
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
I did not implement any outputs yet so should I create a bridge or should I base my outputs on the Avalon-MM interface?
--- Quote End ---
Yes, you could implement your CPU interface according to the Avalon-MM specification.

While working on your CPU, you might want to consider keeping your CPU external to the Qsys system, i.e., the Avalon-MM master interface would be exported to the top-level of the Qsys system.

This allows you to iterate on the CPU design without having to regenerate the Qsys system. Qsys has this annoying feature, where it copies source files into various synthesis and simulation directories. Keeping your CPU external to the Qsys system would avoid having multiple copies of your CPU design files.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
So then to implement the system will I need to use 2 Quartus projects: one for the CPU, and one for the qsys stuff.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
So then to implement the system will I need to use 2 Quartus projects: one for the CPU, and one for the qsys stuff.
--- Quote End ---

No, you just need one project.

You will have a top-level design, and that design will contain two components; your CPU and the Qsys system.

The Qsys system is created using the Qsys GUI. You'd add the Altera-provided IP you want to interface to, and export an Avalon-MM master interface. I believe there is a convenient way to do this, but I forget the details, read the Qsys documentation. In the past I have used an _hw.tcl file to export an interface to the top-level.

You would generate the Qsys system, and it'll create the components that you can then use for synthesis and simulation.

Go through this tutorial and what I am saying should make a little more sense:

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

This tutorial does not have a top-level Avalon-MM interface, but it does show a Qsys system instantiated in a top-level design that contains other components.

Cheers,
Dave

Altera_Forum

Honored Contributor

13 years ago

I have 2 questions:

1. I cant get the mp32 core to work with quartus 11.1. Is there any solutions to the problem that doesnt involve downgrading?

2. Is there any tutorials on the Avalon-MM interface. (Not the actuall specification pdf, but a tutorial)

EDIT: I refreshed the QSYS system and I got this:


Info: Reading index C:/altera/11.1sp2/ip/mp32/components.ipx
Info: C:/altera/11.1sp2/ip/mp32/components.ipx described 6 plugins, 0 paths, in 0.00 seconds
Info: no _hw.tcl package requested, assuming package require -exact sopc 9.0
Info: no _hw.tcl package requested, assuming package require -exact sopc 9.0
Info: no _hw.tcl package requested, assuming package require -exact sopc 9.0
Info: no _hw.tcl package requested, assuming package require -exact sopc 9.0
Info: no _hw.tcl package requested, assuming package require -exact sopc 9.0
Info: no _hw.tcl package requested, assuming package require -exact sopc 9.0

Altera_Forum
Honored Contributor
13 years ago
I decided that I am going to implement the VGA controller first. It reads the buffer from the sdram using DMA, and then outputs it over VGA. How would I go about to design the AVALON controller for it.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
I decided that I am going to implement the VGA controller first. It reads the buffer from the sdram using DMA, and then outputs it over VGA. How would I go about to design the AVALON controller for it.
--- Quote End ---

There is nothing particularly 'special' about the Avalon-MM interface. Its just a set of rules, and you need to create the logic to follow the rules.

The Avalon specification defines the interface and the Verification IP Suite provides bus functional models for each of the protocols. Those BFMs work best from SystemVerilog.

The following tutorial contains a testbench with an Avalon Master BFM:

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

Use that BFM to test your Avalon-MM slave device.

Start by creating a very simple Avalon-MM slave, eg., a single register that can be written and read. If you get stuck, I can dig up an example, but give it a try first, as it will force you to read (and start to understand) the Avalon documentation.

Cheers,
Dave

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Best way to interface my CPU

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