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So then to implement the system will I need to use 2 Quartus projects: one for the CPU, and one for the qsys stuff.
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No, you just need one project.
You will have a top-level design, and that design will contain two components; your CPU and the Qsys system.
The Qsys system is created using the Qsys GUI. You'd add the Altera-provided IP you want to interface to, and export an Avalon-MM master interface. I believe there is a convenient way to do this, but I forget the details, read the Qsys documentation. In the past I have used an _hw.tcl file to export an interface to the top-level.
You would generate the Qsys system, and it'll create the components that you can then use for synthesis and simulation.
Go through this tutorial and what I am saying should make a little more sense:
http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial This tutorial does not have a top-level Avalon-MM interface, but it does show a Qsys system instantiated in a top-level design that contains other components.
Cheers,
Dave
Honored Contributor
