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I am not sure if that will allow me to continually update my CPU without being forced to make a new component every time. Can somebody elaborate the process of making a custom CPU work with QSYS.
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Assuming your CPU has some form of external bus interface that is not quite an Avalon-MM master interface, you will need to create a bridge component that maps your CPU bus into an Avalon-MM interface. That bridge would
export (via conduit signals) your CPU bus to the top-level of the design.
The top-level of the design would contain the Qsys system (which includes the bridge), and your CPU. As you iterate on your CPU design, the Qsys system remains identical.
To design your CPU bus-to-Avalon-MM bridge, you should create a bus functional model (BFM) for your CPU bus. You can then create a testbench for your bridge logic and the Qsys system.
You can then go back to your CPU design, knowing that the Qsys system has already been verified to work with your expected CPU cycles.
Cheers,
Dave
Honored Contributor
