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I did not implement any outputs yet so should I create a bridge or should I base my outputs on the Avalon-MM interface?
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Yes, you could implement your CPU interface according to the Avalon-MM specification.
While working on your CPU, you might want to consider keeping your CPU
external to the Qsys system, i.e., the Avalon-MM master interface would be exported to the top-level of the Qsys system.
This allows you to iterate on the CPU design without having to regenerate the Qsys system. Qsys has this annoying feature, where it copies source files into various synthesis and simulation directories. Keeping your CPU external to the Qsys system would avoid having multiple copies of your CPU design files.
Cheers,
Dave
Honored Contributor
