Best approach for creating clock sources please?

Hello again and more inane questions from yours truly!

I have a design which relies on many different clock sources: A lot of inter-dependent timing going on.

What therefore is the best (or 'proper') approach to creating many different clocking sources (from the same basic clock source input of course).

I know it is not 'good practice' to gate clocks to create another clock which is then used to clock say a latch or a register etc.

So, what is considered a good / acceptable clock source? The output of a state machine perhaps? The output of a counter?

Any guidelines / comments / suggestions much appreciated!

I include below VHDL of something I have written that creates an 8MHz clock from my 24MHz source:

  proc_8MHz : PROCESS (nPowerSettleDelay, M24MHz)
  BEGIN
    IF nPowerSettleDelay='0' THEN
      uM8MHz     <= '1';
      u_nM8MHz   <= '0';
      Next_State <= State_1;
    ELSIF RISING_EDGE(M24MHz) THEN
      CASE Next_State IS
        WHEN State_1 =>
          Next_State <= State_2;
          uM8MHz   <= '1';          --  1
          u_nM8MHz <= '0';          --  0
        WHEN State_2 =>
          Next_State <= State_3;
          uM8MHz   <= '0';          --  0
          u_nM8MHz <= '1';          --  1
        WHEN State_3 =>
          Next_State <= State_1;
          uM8MHz   <= '0';          --  0
          u_nM8MHz <= '0';          --  0
      END CASE;
    END IF;
  END PROCESS proc_8MHz;

Is it 'safe' then to use either the uM8MHz or the nM8MHz signal as clock sources?

Cheers again all,

Andy