Forum Discussion
Altera_Forum
Honored Contributor
11 years agoThe clock source is constant and a 'true' clock.
I think maybe I am implementing the enable signal incorrectly....
proc_Counters : PROCESS(IN_RESETn, M24MHz)
BEGIN
IF IN_RESETn='0' THEN
usg_Counter_7_0 <= (OTHERS => '0');
ELSIF RISING_EDGE(M24MHz) THEN
IF en_uM8MHz ='1' THEN
IF usg_Counter_7_0 = usg_MAXCOUNT THEN
--Reset the counter...
usg_Counter_7_0 <= (OTHERS => '0');
ELSE
--... or increment the counter
usg_Counter_7_0 <= usg_Counter_7_0 + 1;
END IF;
END IF;
END IF;
END PROCESS proc_Counters;
Yes in my sim, I see the counter increasing in bursts.