Honored ContributorHello,
I am trying to build a simple Qsys SoC consisting of a Nios II/e with on-chip memory. I also require to translate the Nios II signals from Avalon to AXI. Is there any IP in Qsys which does this? On exporting the Nios II signals to AXI, these AXI signals would be used with a megawizard-created DDR3 controller.
Honored ContributorNo bridge is required. If the Nios will be an Avalon master connecting to an AXI slave, then the interconnect gets generated automatically to allow for communication between the two.
Honored ContributorHi,
Thank you for your reply. In my case, the AXI slave is a DDR3 SDRAM controller using UniPhy, which is generated in Quartus II using Megawizard. Its essentially a preset framework I don't want to alter. How would I then go about generating the AXI signals for Nios II in Qsys, if the AXI slave is not a part of the Qsys SoC? Thanks, NikhilHonored ContributorI'm not sure why you don't want to just add the memory controller into Qsys, but I believe there is an Avalon to AXI bridge component in Qsys. You would connect the Nios to the Avalon side and export the AXI side to connect to the memory controller outside of Qsys.
Honored ContributorHi,
Thank you so much. I'm not adding the DDR3 memory controller in Qsys because I'm working with a preset Quartus II project which already has a megawizard controller. This controller is being used for a bunch of other functions. Would you happen to know roughly what the Avalon to AXI bridge IP is called in Qsys? Because I'm not able to find anything in Qsys with the required functionality.Honored ContributorYou'll have to build it out of interconnect components:
Avalon master agent -> AXI slave agent -> export AXI interfaceHonored ContributorThank you. I have attached a screenshot of the SoC made in Qsys. On the Avalon MM master, what are cp and rp? And on the AXI slave, what are read_cp, write_cp, read_rp and write_rp? I couldn't find anything on these in the Altera documentation. I find that in Qsys, cp of the Avalon MM master can only be connected to either read_cp or write_cp on the AXI slave, not both. Also only one of read_rp or write_rp on the AXI slave can be connected to rp on the Avalon MM master. So what would be the correct way of doing these connections? Also, when I want Nios II to write something to DDR3, would a simple pointer reference be enough? I apologise for asking so many questions, but I'm quite new to all this.
