Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi,
Thank you for your reply. In my case, the AXI slave is a DDR3 SDRAM controller using UniPhy, which is generated in Quartus II using Megawizard. Its essentially a preset framework I don't want to alter. How would I then go about generating the AXI signals for Nios II in Qsys, if the AXI slave is not a part of the Qsys SoC? Thanks, Nikhil