Avalon mm Master BFM

I tried using your suggestions but the issue still remains. Do you think there's anything further that I could do to address this problem.

Hi,

Since the BFM push command had been tested before without any problem. Seems like the problem is on the custom slave. I mean before is what will happen if you modify the custom slave device with an 8-bit data width and multiple individually addressable 8-bit data registers with adjacent addresses to custom slave device with an 8-bit data width and single addressable 8-bit data registers?

Thanks,

Best Regards,

Sheng

Hi,

Any further update or concern?

Thanks,

Best Regards,

Sheng

I will try your suggestion. Maybe single addressable 8-bit registers could be tested.

Regarding the qwork example that you provided with multiple slave IP's such as on-chip RAM, when I did run the simulation, the readdatavalid is getting asserted after a clock cycle. Hence the data that is being written to RAM will be returned xxxxxxxx's when reaching the BFM master.

Therefore, what component is asserting readdatavalid and how can we remove the delay between readdata signal and readdatavalid signal?

The screenshot 1 below is the console window which reads the data that is being read.

The screenshot 2 below is the problem that I stated above regarding readdatavalid signal.

I haven't made any changes in your program except writing to ON-chip RAM instead of PIO_control.

Hi,

For On-Chip RAM, have to look at the test program in qsys_system_tb_burst.sv. Include that will be able to simulate the On-Chip RAM. The address is addr = ONCHIP_RAM + 4*i; as the symbol width is 8 while the data width is 32.

Thanks,

Best Regards,

Sheng

Any further concern or update?