Occasional ContributorArria5 GX Transceiver Clocking Question, using internal clock on more than 4 transceivers?
Support,
I have a design which is working with 4 transceivers and each transceiver is treated independently from the standpoint of our HDL design. The transceivers are driven on the pins: rx_cdr_refclk and tx_pll_refclk from a AlteraPLL. We are really using the transceivers as PHY only -- this is a completely custom protocol.
I have the need to expand from 4 transceivers to 6 transceivers. I felt I could just expand the number of "by1" transceivers from 4 to 6. But alas QuartusPrim 21.x has other ideas. I believe this is due to the clocks are shared by a group of 4 transceivers but are not shared by all the transceivers on the same side. Yes I am trying to use 6 transceivers on the same side of the die.
In reading through the manual it seem I am attempting to use xN Native Phy clock network. I have read the description but don't understand how to directly implement what is said. What I would like to implement is my one PLL drives all transceivers on a side!
Do I need a second PLL running from the same clock source which generates the same frequencies and attach that to the 2 new transceivers? How do I manage the phase difference of these two transceivers with respect to my RTL which is interfacing via one of the clocks?
I am leveraging an Arria5 development platform and I must use internal clocking because of some external interfaces which are already set up. So I have a lot of limitations on choice of clocks and such -- a limitation that maybe we could overcome but not without much delay and lots of "why" meetings.
Looking for guidance as I believe this comes down to clock management of the transceivers in the Arria5 GX part. It just isn't clear if you are using this in Native PHY mode.
TomT...
