Arria5 GX Transceiver Clocking Question, using internal clock on more than 4 transceivers?

Device: 5AGXFB3H4F35C4

OS: Linux CentOS 7

Tool Version: QuartusPrime 21.1.0.842

This is a development card so the only transceiver pins I can use are as follows:

G3, J3, L3, N3, R3, U3, W3, AA3 -- TX_P

H1, K1, M1, P1, T1, V1, Y1, AB1 -- RX_B

The clock is internally generated, yes I know the Jitter will be higher but that is what I have available. This design uses a home grown protocol so we just need the Transceivers for SERDES operation, we are bypassing much of the logic. I have this working with 4 transceivers but now need to expand to 6 transceivers. That is where the issue resides.

Thanks,

TomT...