Forum Discussion
Hi,
Please specify the data rate, that those transceivers need to run at, as this will also determine what you can use. Unfortunately AVGX doesn't support fb_compensation clocking like in SVGX or AVGZ which is ideal to have always the same phase at startup w.r.t. the reference clock (this is you want I believe). So to have the next best option you would have to use x6 clocking (x6_fPLL) but data rate limited to 3.125 Gbps or xN clocking using CMU PLL (requires 7 channels to clock 6 transmitters) which according to the datasheet is limited to 5 Gbps (but not restricted in Quartus apparently). I suggest you refer to this document which gives all options https://cdrdv2.intel.com/v1/dl/getContent/683573
Thank you
Kshitij Goel
The serial data rate is 2.912Gbps, well within the specification for the device.
So it sounds like I need a different configuration for my Transceivers than I have now to use the x6_fpll which would support attaching up to 8 transceivers from the same internally generated PLL?
I would say there are answers in that manual but they are not organized in a way to answer if you want to use the Transceivers in a not standard way which is what I am trying to do. The questions are hard and the answers are even harder to find.
If I was building something that was using PMA Direct at that data-rate and wanted to use an internally generated 182MHz source clock (x16 to get to 2.912GHz) and connect up to 8 transceivers can I do it with the Pins I mentioned above?
Thanks,
TomT...