Arria5 GX Transceiver Clocking Question, using internal clock on more than 4 transceivers?

Hi,

Please specify the data rate, that those transceivers need to run at, as this will also determine what you can use. Unfortunately AVGX doesn't support fb_compensation clocking like in SVGX or AVGZ which is ideal to have always the same phase at startup w.r.t. the reference clock (this is you want I believe). So to have the next best option you would have to use x6 clocking (x6_fPLL) but data rate limited to 3.125 Gbps or xN clocking using CMU PLL (requires 7 channels to clock 6 transmitters) which according to the datasheet is limited to 5 Gbps (but not restricted in Quartus apparently). I suggest you refer to this document which gives all options https://cdrdv2.intel.com/v1/dl/getContent/683573

Thank you

Kshitij Goel