Forum Discussion
EBoln
Occasional Contributor
Occasional ContributorArria V clock no output dependent(15610)
HI!
i am using arria v for a new project but ran into the following behavior:
- when I only use logic, the clock pin is synthesized successfully
- when I add video ip core to the project, then all the logic connected to this clock pin is not synthesized
Why? Project in attachments(i'm use Q18.1.1)
thank
P.S. on RTL viewer all is OK, but post-mapping clock network is absent
Found a bug in my custom qsys module, the reset was confused
3 Replies
JonWay_alteraFrequent Contributor
Hi EBoln,
There is no attachment. If your project is huge, could you send us a simplified design that shows the problem. Thanks.
EBolnFound a bug in my custom qsys module, the reset was confused
- JonWay_altera
Thanks @EBoln for sharing the root cause of the problem.
