ContributionsMost RecentMost LikesSolutionsRe: mem_reset_n always is low from DDR3 hard controller no, thx Re: mem_reset_n always is low from DDR3 hard controller I changed the core type to soft controller and keep track of mem_reset_n generation. dataout[0] from ARRIAV_DDIO_OUT - mem_reset_n pll_addr_cmd_clk - exist DATAINHI and DATAINLO - 2'b11 ARESET - 1'b0(from ~reset_reg[14]) Why??? Re: mem_reset_n always is low from DDR3 hard controller I create new project with same qsys file with ddr3 controller Re: mem_reset_n always is low from DDR3 hard controller I try to simulate... and all signals correct Re: mem_reset_n always is low from DDR3 hard controller And i try create new qsys with controller Re: mem_reset_n always is low from DDR3 hard controller I copy qsys file with DDR3 controller from CycloneV project to ArriaV project, ofcourse i change FPGA type in qsys file Re: mem_reset_n always is low from DDR3 hard controller At the moment, no, since there were no problems when using the core on Cyclone 5 Re: Ubuntu usb blaster I remind you that I use the same sof file on windows and on linux Re: Ubuntu usb blaster i have 5 Terasic DE0-Nano and 2 Terasic DE2. Re: mem_reset_n always is low from DDR3 hard controllerI am using 18.1.1 and 20.1 standard edition
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