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EBoln's avatar
EBoln
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

mem_reset_n always is low from DDR3 hard controller

Hi, i have ArriaV, DDR3 chips, but after deassert global and soft resets mem_reset_n stay is low. Soft reset generate after 1000 tick on 100MHz clk What else can affect this signal?
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Have you try to simulate your IP with the example design in your simulation?

EBoln's avatar
EBoln
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

At the moment, no, since there were no problems when using the core on Cyclone 5