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EBoln's avatar
EBoln
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

mem_reset_n always is low from DDR3 hard controller

Hi, i have ArriaV, DDR3 chips, but after deassert global and soft resets mem_reset_n stay is low. Soft reset generate after 1000 tick on 100MHz clk What else can affect this signal?
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Thanks for clarifying about your project.

I guess there is no error during the IP generating process and compilation.

But since you're facing some issue with the Arria V device, can you use the example design to simulate your IP in the Arria V?

EBoln's avatar
EBoln
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I try to simulate... and all signals correct

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Great!

    Can you check the connection between your IP and your design?

    And compare it with the example design.

    • EBoln's avatar
      EBoln
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      I create new project with same qsys file with ddr3 controller