arrays in vhdl

the code you have posted is verilog and you dont show how randh and address are declared in verilog.

data <= walls_rand( to_integer( unsigned(randh(1 downto 0) & address(3 downto 0) ) );

--- Quote Start ---

the code you have posted is verilog and you dont show how randh and address are declared in verilog.

data <= walls_rand( to_integer( unsigned(randh(1 downto 0) & address(3 downto 0) ) );

--- Quote End ---

whole verilog code as follow

module wall_generator(

input clk,

input [63:0]rand,

input hold,

input [5:0]address,

output reg [5:0]data

);

reg [63:0]randh;

reg [5:0]walls_rand[0:63];

reg [5:0]walls_alt[0:63];

reg [5:0]walls_maze[0:127];

always @(posedge clk) begin

if(!hold) begin

randh <= rand;

end

end

always @* begin

case(address[5:4])

2'd0: begin

data <= walls_rand[{randh[1:0],address[3:0]}];

end

2'd1: begin

data <= walls_alt[{randh[3:2],address[3:0]}];

end

2'd2: begin

data <= walls_rand[{randh[5:4],address[3:0]}];

end

2'd3: begin

data <= walls_maze[{randh[8:6],address[3:0]}];

end

endcase

end

whole verilog code as follow:

module wall_generator(

input clk,

input [63:0]rand,

input hold,

input [5:0]address,

output reg [5:0]data

);

reg [63:0]randh;

reg [5:0]walls_rand[0:63];

reg [5:0]walls_alt[0:63];

reg [5:0]walls_maze[0:127];

always @(posedge clk) begin

if(!hold) begin

randh <= rand;

end

end

always @* begin

case(address[5:4])

2'd0: begin

data <= walls_rand[{randh[1:0],address[3:0]}];

end

2'd1: begin

data <= walls_alt[{randh[3:2],address[3:0]}];

end

2'd2: begin

data <= walls_rand[{randh[5:4],address[3:0]}];

end

2'd3: begin

data <= walls_maze[{randh[8:6],address[3:0]}];

end

endcase

end