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Altera_Forum's avatar
Altera_Forum
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9 years ago

arrays in vhdl

how to do following operation in vhdl ? data <= walls_rand[{randh[1:0],address[3:0]}]; * here walls_rand is an array and data,randh,address are std_logic vectors *reg [5:0]walls_rand[0:6...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

the code you have posted is verilog and you dont show how randh and address are declared in verilog.

data <= walls_rand( to_integer( unsigned(randh(1 downto 0) & address(3 downto 0) ) );