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yelen's avatar
yelen
Icon for New Contributor rankNew Contributor
2 years ago

array value miss of add

When we used the command line to simulate our project, these files did not run normally, causing the output variable 'Hdl_out' during simulation to produce erroneous results that were not in line with our expected design. This variable came from the ADD output module of the previous level. The `Subsystem_org.v` file is set in the unlock file for the test. In order to reproduce the problem in the future, we have attached the required source files to the submission materials. We hope this can help you find and solve this problem.

Hdl

2 Replies

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hi,

    I had compiled successfully all the files and testbench straight away in simulator. I notice there're undefined (xx) problem with the previous variables already attached screenshot. Since most of the signals are inter-related, probably have to check back which function signals output cause the conflict.

    Thanks,

    Sheng

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    Do you have any further update or concern on this thread?


    Thanks,

    Regards,

    Sheng