Anybody booting using QYS from EPCS?

I haven't switched to QSys yet as some of our tools only work with SOPC. But did you check that the conversion was done properly from SOPC to QSYS? Are both the data and instruction masters connected to the EPCS controller, and is the Nios CPU reset address set to the EPCS?

The bootloader is the same in both cases and I don't see why the QSys architecture would change anything.

You can set up some SignalTap probes to monitor the CPU's avalon busses and see what it is trying to do. SignalTap can be configured to trigger automatically at power up, so you can see what happens when the CPU gets out of reset.

Some points to remember, the projects run fine under the debugger. So the two conversions and the one native from scratch qsys run fine. There is no run time issue here. They just won't boot from epcs.

I can't signal tap or anything else because the sof is never loaded properly in the first place.

The fact that the CPU was running fine from the debugger was the reason why I suggested to check the CPU's reset vector and connection to the EPCS controller. The CPU can run fine from the debugger even without those two points, but wouldn't be able to boot.

Are you sure about your LED test? Isn't there anything that could make them turn off immediately after the FPGA is configured? I find it odd that using QSys would make the flashed EPCS image unloadable for the FPGA. Did you check the FPGA's config and status pins? Can you communicate with the CPU over JTAG (either terminal or software upload) without uploading a .sof image through JTAG first?

Yes the leds are basic pll lock and just for sure one is tied on. They never come on.

and of course I can't talk to the cpu because there is no cpu yet.

Did you check the FPGA's status pin?

Is the pll inside the Qsys/ SOPC component or is it instantiated outside (from HDL code or the megawizard)?

Can you change the configuration so that it always turn the led on, whatever the pll status is? It will let you know if it is really a configuration problem or if the pll doesn't lock, for whatever reason.

I have switched to QSYS and it works fine. Nios boots from epcs. Using Terasic De0-nano.

BUT I think I have seen the exact same problem as reported here. The cure for my case is found in my notes from back then - listed below. There are information already mentioned in this thread but I list it all for completeness. But check out point 5 if it applies to you as well. That was the crucial point for my case at least.

Regards Henning

1. In QSYS, make sure the EPCS device is accessible from both data and instruction port of NIOS!!!

2. Set the reset vector to the the BASE address of the EPCS device as seen from the NIOS in qsys builder. Offset is set to 0. See Figure 1. See also an458 and Figure 4 below.

3. When nios enters reset it excutes the rom code which is compiled into the epcs component interface. This code which is a little less than 1kB is boot code which reads the image from the epcs and puts it into the volatile ram as defined in the linker (See the bsp editor). The epcs interface is 2kB in total. The upper 1kB is used to command the flash. This information is important to remember when you prepare the boot image using the flash programmer: you should not include any boot code!

4. Make sure all the binary images are set to be located in volatile ram, as this invokes the boot copier if the ram in question needs initialization data. This is typically the .text, .rodata, .bss etc.

5. Ensure that log output to jtag port is NOT enabled in Eclipse build. This is setup in the Board Support Editor under Main->Settings->advanced->hal->LogPort (cost me 2 days lost work). The processor halts when it does not get handshake from the jtag-attached host device, and consequently it appears to not run. (at least that is what I think is happening because once it worked I lost interest in finding out what exactly was going on). It is probably also a good idea to remove jtag_uart as stdio, although it is seen to work anyway when not removing this in BSP editor. Anyway jtag-uart makes little sense when running stand-alone from flash.

6. In Board Support Editor under Main->Settings->advanced->hal->linker Remove the ticks marks in all the 5 options: Allow_code_at_reset, enable_alt_load etc. (Not sure what this does, but found this in an altera application note. In addition I am not sure if this will actually make a difference)