Anybody booting using QYS from EPCS?

I haven't switched to QSys yet as some of our tools only work with SOPC. But did you check that the conversion was done properly from SOPC to QSYS? Are both the data and instruction masters connected to the EPCS controller, and is the Nios CPU reset address set to the EPCS?

The bootloader is the same in both cases and I don't see why the QSys architecture would change anything.

You can set up some SignalTap probes to monitor the CPU's avalon busses and see what it is trying to do. SignalTap can be configured to trigger automatically at power up, so you can see what happens when the CPU gets out of reset.