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Altera_Forum's avatar
Altera_Forum
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13 years ago

Anybody booting using QYS from EPCS?

I have three boards, one old and two new boards. One has Cyclone II, the other is Cyclone IV and the last is a Stratix III. They all three boot from EPCS fine if it is compiled from SOPC. None of the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The fact that the CPU was running fine from the debugger was the reason why I suggested to check the CPU's reset vector and connection to the EPCS controller. The CPU can run fine from the debugger even without those two points, but wouldn't be able to boot.

Are you sure about your LED test? Isn't there anything that could make them turn off immediately after the FPGA is configured? I find it odd that using QSys would make the flashed EPCS image unloadable for the FPGA. Did you check the FPGA's config and status pins? Can you communicate with the CPU over JTAG (either terminal or software upload) without uploading a .sof image through JTAG first?