Another beginners question

Hi Don,

Don't start with Qsys, start with straight VHDL or Verilog. Do not even bother with schematics, start with an HDL.

An FPGA design consists of;

1. Your hardware design (in VHDL or Verilog)

2. Your device assignment (the FPGA you are using)

3. Your pin assignments (CRITICALLY IMPORTANT)

4. Your timing assignments

You can get away with HDL and pin assignments to start with, and Quartus will generate some warning messages about a missing clock constraint. You can safely ignore that for beginner designs, but not for long!

Start out by simply routing the switches to the LEDs, eg., your HDL will look something like

-- Entity (VHDL) or Module (Verilog) definition (ports on the component)
-- Switch inputs
-- LED outputs
-- Body of the code with ...
leds <= switches; -- VHDL
assign leds = switches; -- Verilog

I deliberately left out the syntax details. You can figure those out.

Hint: the Quartus editor has templates that you can insert and then fill in the details.

Use the assignments editor to create the pin constraints.

When you synthesize the design, check the .pin file has pin assignments that matches the DE2-115.

If you are worried you will damage your board, create a .qar file, and email it to me (use my Altera Forum name), and I'll take a look at the design.

Cheers.

Dave

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I would add that you do make a schematic design, but on paper. First think about the hardware you want, then write HDL to make it.

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That is a good point.

If you cannot draw a block diagram, or the block diagram looks too complicated, then often your design is too complicated.

I often apply this philosophy to my state machine designs; I get them working, then as I document them using Algorithmic State Machine (ASM) charts, I often realize that I can simplify them. (Often I can simply copy a working design and modify it too, or generalize it to cover a new use case).

Don - there are plenty of resources on this page (they're not all beginner level, but you can at least see examples of code and documentation).

https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

Cheers,

Dave

Hi Dave

Thanks for the reply

Basically what you suggest is what I have been doing

I decided at the beginning to use VHDL rather than verilog and used this bit of code

library ieee;
use ieee.std_logic_1164.all;
entity light2 is
	port
	(x1, x2	: in  std_logic;
	f	: out std_logic);
	
end light2;
architecture LogicFunction of light2 is
begin
	f<= (x1 and not x2) or ( not x1 and x2);
END LogicFunction ;

But first I did it in Schematic which for a simple code like this was uneccesary but had it been more complex

then for a beginner it would be easier.

The reason I asked my question , which I think you missed was to ask if it is possible to get VHDL from a schematic or Schematic from

VHDL so that should I wish to to code something that was more complex I could first do it in schematic and then if its possible convert that to VHDL

so that I could see what I should actually write in VHDL code

and conversely if I saw someone elses code in VHDL that was beyond my understanding then if its possible to convert it to a schematic I might better understand what is going on .

So is it possible, will Quatus II convert VHDL to schematic or the other way round schematic to VHDL ?

Regards

Don

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Hi Don,

Don't start with Qsys, start with straight VHDL or Verilog. Do not even bother with schematics, start with an HDL.

An FPGA design consists of;

1. Your hardware design (in VHDL or Verilog)

2. Your device assignment (the FPGA you are using)

3. Your pin assignments (CRITICALLY IMPORTANT)

4. Your timing assignments

You can get away with HDL and pin assignments to start with, and Quartus will generate some warning messages about a missing clock constraint. You can safely ignore that for beginner designs, but not for long!

Start out by simply routing the switches to the LEDs, eg., your HDL will look something like

-- Entity (VHDL) or Module (Verilog) definition (ports on the component)
-- Switch inputs
-- LED outputs
-- Body of the code with ...
leds <= switches; -- VHDL
assign leds = switches; -- Verilog

I deliberately left out the syntax details. You can figure those out.

Hint: the Quartus editor has templates that you can insert and then fill in the details.

Use the assignments editor to create the pin constraints.

When you synthesize the design, check the .pin file has pin assignments that matches the DE2-115.

If you are worried you will damage your board, create a .qar file, and email it to me (use my Altera Forum name), and I'll take a look at the design.

Cheers.

Dave

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If you go to tools -> netlist veiwer -> RTL view that will give you a schematic view of the design at the RTL level. The post map viewer will give you a view of the design at the primitives level (luts and registers) - these are not the same as the schematic entry mode.

Quartus can convert schematics that you draw to VHDL - but I dont think you'll like reading the VHDL that is generates much. It is only really meant for simulation.

But as other have said, before you write any code, you need to draw your schematic on paper. When you get used to this, and you can think in schematics, then you can move more freely with the code. But with any design, the documentation should break the design down as much as possible before any code is written.

Thanks for all the replies .

I can see the sense in what you are all saying , especially about getting it down on paper first so I can see where I am going

I did try what Tricky said using tools/netlist viewer/RTL and yes it did give me a view of a schematic that might let me better understand someone elses code

and I did try going the otherway converting schematic to VHDL but the code was a bit weird , it put in lots of lines about synthesized wires , which I hadnt used in my VHDL code

I think the hardest part for me right now is thinking of something to try to code that is simple enough for a raw beginner like me , but

interesting enough for me to want to do it

Don

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Thanks for all the replies .

I can see the sense in what you are all saying , especially about getting it down on paper first so I can see where I am going

I did try what Tricky said using tools/netlist viewer/RTL and yes it did give me a view of a schematic that might let me better understand someone elses code

and I did try going the otherway converting schematic to VHDL but the code was a bit weird , it put in lots of lines about synthesized wires , which I hadnt used in my VHDL code

I think the hardest part for me right now is thinking of something to try to code that is simple enough for a raw beginner like me , but

interesting enough for me to want to do it

Don

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This "synthesised_wires" are just signals to connect the things together. Auto Generated code is generally a mess and not very nice to read, so dont bother (write it yourself)

Altera has plenty of guidelines how to write code to infer all the primitives in different modes - have a read of the HDL coding guide (section 12): https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf

My first HDL project was my final year project. We had been given an "idealised" CPU instruction set the year before, and the project was to implement a CPU that used it. It was a simple fixed width instruction based, with very little in the way of complicated instructions- load A, load B - Add A, B, Jump etc. But it got me understanding HDL (with a lot of help from a PhD friend).

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https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

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This is a great link! Very informative!

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This is a great link! Very informative!

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I am sure you are right but its a little ( make that a lot ) too advanced for me right now , but I have bookmarked it for the future

and am always glad of links to stuff that will help me out so allthough I am not able to use this link yet , hopefully one day I will be

I have only started with FPGA for about 2 days now and most of that time has been spent , loading Quartus II V 15 software onto my PC , arranging directories to store books, manuals, Tutorials etc .

And the rest of the time , watching online tutorials , printing out usefull charts ( like the pin assignments for me DE2-115 board )

It doesnt help either that I am now a pensioner and so things dont sink in my brain as quick as they did when younger. Programming has not been something I have done for a living

I am just an electronics enthusiast thats hoping to pick up enough about FPGAs to make it interesting . Its also a way to keep my brain active

My first mistake was downloading every tutorial I could find . only to find some were for Quartus II versions prior to 15 and sometimes they have things no longer found in the newer version or has been replaced

by a better alternative . If I were more knowlegable I am sure I could work out ways around this but being a raw beginner I cant so I have now only kept the tutorials for version 15

second problem was some tutorials were using Verilog and some VHDL . Again if I was younger or more experienced in FPGAs I might have a chance at learning two languages , but for me one is more than enough to cope with and so I settled on VHDL . From what I read this is what most europeans use.

So any help , links , tips tutorials or ideas for something to try to code ( that are suitable for a complete beginner and use VHDL on Quartus II V 15) I would be glad to receive them

I know its only easy but for my first project I am going to try to use the switches and leds on the DE2-115 to simulate simple gates , AND OR NAND NOR XOR etc

if nothing else it will start to teach me the correct syntax for writing entities and architectures and to find my way around the Quartus GUI

Regards

Don