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Thanks for all the replies .
I can see the sense in what you are all saying , especially about getting it down on paper first so I can see where I am going
I did try what Tricky said using tools/netlist viewer/RTL and yes it did give me a view of a schematic that might let me better understand someone elses code
and I did try going the otherway converting schematic to VHDL but the code was a bit weird , it put in lots of lines about synthesized wires , which I hadnt used in my VHDL code
I think the hardest part for me right now is thinking of something to try to code that is simple enough for a raw beginner like me , but
interesting enough for me to want to do it
Don
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This "synthesised_wires" are just signals to connect the things together. Auto Generated code is generally a mess and not very nice to read, so dont bother (write it yourself)
Altera has plenty of guidelines how to write code to infer all the primitives in different modes - have a read of the HDL coding guide (section 12):
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf My first HDL project was my final year project. We had been given an "idealised" CPU instruction set the year before, and the project was to implement a CPU that used it. It was a simple fixed width instruction based, with very little in the way of complicated instructions- load A, load B - Add A, B, Jump etc. But it got me understanding HDL (with a lot of help from a PhD friend).
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