Another beginners question

Hi Dave

Thanks for the reply

Basically what you suggest is what I have been doing

I decided at the beginning to use VHDL rather than verilog and used this bit of code

library ieee;
use ieee.std_logic_1164.all;
entity light2 is
	port
	(x1, x2	: in  std_logic;
	f	: out std_logic);
	
end light2;
architecture LogicFunction of light2 is
begin
	f<= (x1 and not x2) or ( not x1 and x2);
END LogicFunction ;

But first I did it in Schematic which for a simple code like this was uneccesary but had it been more complex

then for a beginner it would be easier.

The reason I asked my question , which I think you missed was to ask if it is possible to get VHDL from a schematic or Schematic from

VHDL so that should I wish to to code something that was more complex I could first do it in schematic and then if its possible convert that to VHDL

so that I could see what I should actually write in VHDL code

and conversely if I saw someone elses code in VHDL that was beyond my understanding then if its possible to convert it to a schematic I might better understand what is going on .

So is it possible, will Quatus II convert VHDL to schematic or the other way round schematic to VHDL ?

Regards

Don

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Hi Don,

Don't start with Qsys, start with straight VHDL or Verilog. Do not even bother with schematics, start with an HDL.

An FPGA design consists of;

1. Your hardware design (in VHDL or Verilog)

2. Your device assignment (the FPGA you are using)

3. Your pin assignments (CRITICALLY IMPORTANT)

4. Your timing assignments

You can get away with HDL and pin assignments to start with, and Quartus will generate some warning messages about a missing clock constraint. You can safely ignore that for beginner designs, but not for long!

Start out by simply routing the switches to the LEDs, eg., your HDL will look something like

-- Entity (VHDL) or Module (Verilog) definition (ports on the component)
-- Switch inputs
-- LED outputs
-- Body of the code with ...
leds <= switches; -- VHDL
assign leds = switches; -- Verilog

I deliberately left out the syntax details. You can figure those out.

Hint: the Quartus editor has templates that you can insert and then fill in the details.

Use the assignments editor to create the pin constraints.

When you synthesize the design, check the .pin file has pin assignments that matches the DE2-115.

If you are worried you will damage your board, create a .qar file, and email it to me (use my Altera Forum name), and I'll take a look at the design.

Cheers.

Dave

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