Another beginners question

Hi Don,

Don't start with Qsys, start with straight VHDL or Verilog. Do not even bother with schematics, start with an HDL.

An FPGA design consists of;

1. Your hardware design (in VHDL or Verilog)

2. Your device assignment (the FPGA you are using)

3. Your pin assignments (CRITICALLY IMPORTANT)

4. Your timing assignments

You can get away with HDL and pin assignments to start with, and Quartus will generate some warning messages about a missing clock constraint. You can safely ignore that for beginner designs, but not for long!

Start out by simply routing the switches to the LEDs, eg., your HDL will look something like

-- Entity (VHDL) or Module (Verilog) definition (ports on the component)
-- Switch inputs
-- LED outputs
-- Body of the code with ...
leds <= switches; -- VHDL
assign leds = switches; -- Verilog

I deliberately left out the syntax details. You can figure those out.

Hint: the Quartus editor has templates that you can insert and then fill in the details.

Use the assignments editor to create the pin constraints.

When you synthesize the design, check the .pin file has pin assignments that matches the DE2-115.

If you are worried you will damage your board, create a .qar file, and email it to me (use my Altera Forum name), and I'll take a look at the design.

Cheers.

Dave