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dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago
Solved

AN803 run in Quartus 21.3

Dear Support/Expert

I try to run AN803 in Quartus Pro 21.3. there are few modules are protected. for example

# ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region

Did I make some mistake while generate the HDL? everything else seems OK.

if I open the file, it looks like this, how to make this file pass simulation vlog?

Thank you,

David

`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "10.4d"
`pragma protect author = "Altera"
`pragma protect data_method = "aes128-cbc"
`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
`pragma protect encoding = (enctype = "base64", line_length = 64, bytes = 128), key_block
G58SXJEJjEM6j+Np8b9N51BdY9eRlf/EorUPhxBzT25xpzVl6poXs80PEzQ7+pGp
O3azt17BiwVhNOcyYfWTIvBSVVmhSUCeB3fyFcNcWWHR65Wo6z7gR30Emh+Ip6R9
5Z0mGIX5KDm85aTkeXWnQnX0VxIweS8cn4jjjXCZla0=
`pragma protect encoding = (enctype = "base64", line_length = 64, bytes = 20928), data_block
rIx7dM7yE5TVeBGlNBpoBiIEy0CD8RWTPLPtWS+EkT9xrCLY2x+/vCQc8aR1xu3g
QOEMrHmN30QSL3nenz3MJFmos1hTOB2N4t6m5H/51i5uXqKJrNZzZFv2iZqHc1/s
9Xsklxz9kVKLojkVc30UM5sJzxw0qlfYuyCljsKgW52ajY86FOmzJ0aqscyP7qcS
0wr8dZKShNJ3earfrNoyJA9mzX9VDC8PDRw9waSTSKTf//VgXTawoVYLCPHmHtwN
hhPOcFxpeGh/H9pj6Rgqz2HFj99cV+43QaGMQro/jRhntKo4aJontvm+/s8mPwWj
L/QoQYJD7XWqJH0RYf/gSKyo6POw20Ufvz46wyvc+OAyb4DexYchu2mleip13wjx
jNVllOioL3EXTHZgSH8SfkaADlp689t0/lq6qw08QHinXvad4aM8u0gRr5qh3/1A
ISZGieJsRSddvVzu86M9WGeLDHByQWjkwZWXonHXS5NYhMVAp96eWeRrixajIh/t
It8olKVhVxaoaNTiMlTkegXAGcBHuR0XWwagLiU1Mc/lGGUnMuC9SbAnaGtfog4C
p78ZNzlRpya6Lm5wRLizsfYanAA+R4YB0VuDHYekm4XK41QPp643mcwgjOvU3Tvy
IPkus2Lx/LL7PF4KyqlM1k6qXhEHJxBRXsfYpxf/OIAh15jjbpV/3aYjeFjdwEAe
uCq/kLtt632uHtxpWxWlRig+wXgdjaVTUBb7f18HoKFjlMGzPpFrAPkmURGEZXHY

  • SyafieqS's avatar
    SyafieqS
    3 years ago

    Hi David,


    Apologize for the late response as I had been busy on other stuff.

    May I know if there is any update/progress you can share on the platform system simulation and the example design


12 Replies

  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    4 years ago

    More information,

    I downloaded AN803 Pro 17.1 version. and did an auto upgrade to 21.3. and then follow the AN803 instruction, step by step.

    I found that the .tcl file provided not working very well. it claims a lot of file not found. so I add a lot of vlog manually into the run_tb_top.tcl. now if I do this .tcl I got this screen.

    I know the Jesd204b core is a license core. the data sheet claim it should be able to be simulated without license. I guess I did something wrong, I don't expect you help me figure out what is wrong. I hope you can help me confirm that a successful simulation doesn't need license.

    by the way, I am reading <<ug-dex-a10-jesd204b-683113-667114>> and <<ug_jesd204b-683442-667137>>.

    I think an803 is a very practical example, to understanding the Quartus, Questa, Jesd204B, it will be great if there is a updated version for 21.3.

    I hope your help can provide a short cut.

    thank you very much,

    #.........

    #.........

    # [exec] elab_debug
    # vsim -voptargs="+acc" -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L twentynm_ver -L twentynm_hssi_ver -L twentynm_hip_ver -L altera_gpio_core20_2100 -L altera_gpio_2100 -L altera_jesd204_se_outbuf_1bit -L altera_jesd204_ed_qsys_TX_link_clk -L altera_reset_controller_1921 -L altera_jesd204_ed_qsys_TX_reset_controller_0 -L altera_reset_sequencer_1920 -L altera_jesd204_subsystem_TX_reset_seq -L altera_jesd204_subsystem_TX_frame_clk -L altera_jesd204_subsystem_TX_link_clk -L altera_avalon_pio_1913 -L altera_jesd204_ed_qsys_TX_pio_status -L altera_avalon_mm_bridge_2001 -L altera_jesd204_subsystem_TX_mm_bridge -L altera_xcvr_reset_control_1911 -L altera_jesd204_subsystem_TX_xcvr_reset_control_0 -L altera_jesd204_ed_qsys_TX_frame_clk -L altera_jesd204_ed_qsys_TX_device_clk -L altera_jesd204_subsystem_TX_mgmt_clk -L altera_jesd204_subsystem_TX_tx_link_reset_n_0 -L altera_jesd204_ed_qsys_TX_pio_control -L altera_jesd204_subsystem_TX_tx_frame_reset_n_0 -L altera_jesd204_subsystem_TX_device_clk -L altera_jesd204_ed_qsys_TX_JTAG_reset -L altera_jesd204_ed_qsys_TX_mgmt_clk -L altera_iopll_1931 -L altera_jesd204_ed_qsys_TX_core_pll -L altera_avalon_spi_1911 -L altera_jesd204_ed_qsys_TX_spi_0 -L altera_common_sv_packages -L altera_avalon_mm_master_bfm_191 -L altera_jesd204_ed_qsys_TX_mm_master_bfm_0 -L altera_xcvr_atx_pll_a10_191 -L altera_jesd204_ed_qsys_TX_xcvr_atx_pll_0 -L altera_jesd204_tx_191 -L altera_jesd204_tx_mlpcs_191 -L altera_jesd204_phy_adapter_xs_191 -L altera_xcvr_native_a10_191 -L altera_jesd204_phy_191 -L altera_jesd204_1920 -L altera_jesd204_subsystem_TX_altera_jesd204_TX -L altera_merlin_master_translator_191 -L altera_merlin_slave_translator_191 -L altera_merlin_master_agent_191 -L altera_merlin_slave_agent_191 -L altera_avalon_sc_fifo_1930 -L altera_merlin_router_1920 -L altera_merlin_traffic_limiter_191 -L altera_avalon_st_pipeline_stage_1920 -L altera_merlin_burst_adapter_1921 -L altera_merlin_demultiplexer_1921 -L altera_merlin_multiplexer_1921 -L altera_mm_interconnect_1920 -L altera_jesd204_subsystem_TX -L altera_jesd204_ed_qsys_TX tb_top
    # Start time: 08:33:01 on Jan 22,2022
    # ** Note: (vsim-3812) Design is being optimized...
    # ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
    # ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
    # ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
    # ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
    # ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
    # ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
    # ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_rx_mlpcs.v(12): in protected region
    # ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_rx_mlpcs.v(12): in protected region
    # Optimization failed
    # ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1455, Warnings=0.
    # Error loading design
    # Error: Error loading design
    # Pausing macro execution
    # MACRO ./run_tb_top.tcl PAUSED at line 167

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi David,


    Jesd204 IP need license to be simulated otherwise you wont be able to pass the compilation which produce netlist vo/vho needed by the simulator.


    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      4 years ago

      I thought the license only control the generation of the compile output, didn't expect the license will block the simulation. then there will be a chick and egg problem, how do the customer know the IP is working before purchasing the license, as I know the license is very expensive.

      out team did purchase one copy of the Jesd204B license, in this simulation case, how to disable the simulation protection. could you please give me the link to the user manual or data sheet that talking about the protection and active the license to do the simulation.

      Thank you,

      David

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    David,


    That is true, you only need to purchase a full production license for licensed Intel FPGA IP cores

    after completing hardware testing and you are ready to use the IP in production. The

    rest of the time, you can use the Intel FPGA IP Evaluation Mode feature to evaluate IP

    cores. During Intel FPGA IP Evaluation Mode, the Intel Quartus Prime Compiler only generates a time-limited device programming file (<project name>_time_limited.sof) that expires at the time

    limit. You can refer to Intel® FPGA Software Installation and Licensing for more detail.



  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Sun,


    May I know if you are able to simulate the IP?

    Any update on the script etc?


    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      4 years ago

      Hi SyafieqS,

      Thank you for asking. I couldn't simulate the IP. I have a project to implement ultrasound system based on Arria 10 development kits.

      the initial design is from TI demo project. first I plan to create a system simulation platform. I have an I2C module as command input interface. now it is working. So I can visit the FPGA register through the I2C master module. the Nios2 is working in the simulation platform too, I can set the FPGA IO through the Nios2 program. I still have few function blocks to overcome.

      1 is the DDR, functional module. 1 is the Jesd interface module. 1 is PCIe or USB3, FX3 interface.

      now I am struggling with the intel AN812, I downloaded Qsys_pro_tutorial_design_arria_10_17p0. I loaded on the dev board and it working.

      I have been working for several days to create an simulation, but still not successful. for some reason, I couldn't see any toggling on the CPU data and instruction bus. I can see the nios2 ram with program like contents. and both reset and clock are OK. for a generic cpu, it should start read and write the memory after release the reset. don't know why this one doesn't.

      once I can run DDR interface, I will go back to AN803. if you can provide me some suggestion on AN803, I can work on it first, and visit AN812 later. it is a long way to go, but I already far from the start point.

      Intel tools and everything are so powerful, so it is reasonable for a painful learning curve.

      Thank you vey much,

      David

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi David,


    Thank you for the brief and attachment and one concern here:

    "I loaded on the dev board and it working. I have been working for several days to create an simulation, but still not successful"

    - You mean the hardware is working correctly including the cpu data and instruction bus but not in simulation, am I right?


    If you can provide me some suggestion on AN803

    - Let me check internally and let you know any findings.



    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      4 years ago

      Hi SyafieqS

      Yes, you are right, I can download the AN803 sof to the board, and seems it is working. but the goal is not to make it working, is to use it as an example to learn how to use it. for final design, I need do some system level simulation, I hope I can build a JESD204B simulation environment, because it will be hard and time consuming to troubleshoot it directly on the board, even with signal tap tools.

      I almost completed most of the functional module, I can see Nios2 running, spi interface working. so, I am ready to work on the most difficult part.

      The FPGA design and tools are becoming so complicate.

      Thank you very much.

      David

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hi David,


    Apologize for the late response as I had been busy on other stuff.

    May I know if there is any update/progress you can share on the platform system simulation and the example design


  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    3 years ago

    Hi SyafieqS,

    Thank you very much for the following up, I think may be I didn't repeat the instruction correctly. after I tried few more times, I can do simulation now.

    Best Regards,

    David

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.