AN803 run in Quartus 21.3

More information,

I downloaded AN803 Pro 17.1 version. and did an auto upgrade to 21.3. and then follow the AN803 instruction, step by step.

I found that the .tcl file provided not working very well. it claims a lot of file not found. so I add a lot of vlog manually into the run_tb_top.tcl. now if I do this .tcl I got this screen.

I know the Jesd204b core is a license core. the data sheet claim it should be able to be simulated without license. I guess I did something wrong, I don't expect you help me figure out what is wrong. I hope you can help me confirm that a successful simulation doesn't need license.

by the way, I am reading <<ug-dex-a10-jesd204b-683113-667114>> and <<ug_jesd204b-683442-667137>>.

I think an803 is a very practical example, to understanding the Quartus, Questa, Jesd204B, it will be great if there is a updated version for 21.3.

I hope your help can provide a short cut.

thank you very much,

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# [exec] elab_debug
# vsim -voptargs="+acc" -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L twentynm_ver -L twentynm_hssi_ver -L twentynm_hip_ver -L altera_gpio_core20_2100 -L altera_gpio_2100 -L altera_jesd204_se_outbuf_1bit -L altera_jesd204_ed_qsys_TX_link_clk -L altera_reset_controller_1921 -L altera_jesd204_ed_qsys_TX_reset_controller_0 -L altera_reset_sequencer_1920 -L altera_jesd204_subsystem_TX_reset_seq -L altera_jesd204_subsystem_TX_frame_clk -L altera_jesd204_subsystem_TX_link_clk -L altera_avalon_pio_1913 -L altera_jesd204_ed_qsys_TX_pio_status -L altera_avalon_mm_bridge_2001 -L altera_jesd204_subsystem_TX_mm_bridge -L altera_xcvr_reset_control_1911 -L altera_jesd204_subsystem_TX_xcvr_reset_control_0 -L altera_jesd204_ed_qsys_TX_frame_clk -L altera_jesd204_ed_qsys_TX_device_clk -L altera_jesd204_subsystem_TX_mgmt_clk -L altera_jesd204_subsystem_TX_tx_link_reset_n_0 -L altera_jesd204_ed_qsys_TX_pio_control -L altera_jesd204_subsystem_TX_tx_frame_reset_n_0 -L altera_jesd204_subsystem_TX_device_clk -L altera_jesd204_ed_qsys_TX_JTAG_reset -L altera_jesd204_ed_qsys_TX_mgmt_clk -L altera_iopll_1931 -L altera_jesd204_ed_qsys_TX_core_pll -L altera_avalon_spi_1911 -L altera_jesd204_ed_qsys_TX_spi_0 -L altera_common_sv_packages -L altera_avalon_mm_master_bfm_191 -L altera_jesd204_ed_qsys_TX_mm_master_bfm_0 -L altera_xcvr_atx_pll_a10_191 -L altera_jesd204_ed_qsys_TX_xcvr_atx_pll_0 -L altera_jesd204_tx_191 -L altera_jesd204_tx_mlpcs_191 -L altera_jesd204_phy_adapter_xs_191 -L altera_xcvr_native_a10_191 -L altera_jesd204_phy_191 -L altera_jesd204_1920 -L altera_jesd204_subsystem_TX_altera_jesd204_TX -L altera_merlin_master_translator_191 -L altera_merlin_slave_translator_191 -L altera_merlin_master_agent_191 -L altera_merlin_slave_agent_191 -L altera_avalon_sc_fifo_1930 -L altera_merlin_router_1920 -L altera_merlin_traffic_limiter_191 -L altera_avalon_st_pipeline_stage_1920 -L altera_merlin_burst_adapter_1921 -L altera_merlin_demultiplexer_1921 -L altera_merlin_multiplexer_1921 -L altera_mm_interconnect_1920 -L altera_jesd204_subsystem_TX -L altera_jesd204_ed_qsys_TX tb_top
# Start time: 08:33:01 on Jan 22,2022
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
# ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
# ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
# ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
# ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
# ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v(12): in protected region
# ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_rx_mlpcs.v(12): in protected region
# ** Error: C:/FPGA/arria10devkit/AN803_sync_Multi-link_jesd204b/ed_sim/testbench/models/ip/altera_jesd204_subsystem_RX/altera_jesd204_subsystem_RX_altera_jesd204_RX/altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_rx_mlpcs.v(12): in protected region
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1455, Warnings=0.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run_tb_top.tcl PAUSED at line 167